Struct d1_pac::audio_codec::ac_adc_fifoc::W
source · pub struct W(/* private fields */);
Expand description
Register ac_adc_fifoc
writer
Implementations§
source§impl W
impl W
sourcepub fn adc_fifo_flush(&mut self) -> ADC_FIFO_FLUSH_W<'_, 0>
pub fn adc_fifo_flush(&mut self) -> ADC_FIFO_FLUSH_W<'_, 0>
Bit 0 - ADC FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’.
sourcepub fn adc_overrun_irq_en(&mut self) -> ADC_OVERRUN_IRQ_EN_W<'_, 1>
pub fn adc_overrun_irq_en(&mut self) -> ADC_OVERRUN_IRQ_EN_W<'_, 1>
Bit 1 - ADC FIFO Overrun IRQ Enable
sourcepub fn adc_irq_en(&mut self) -> ADC_IRQ_EN_W<'_, 2>
pub fn adc_irq_en(&mut self) -> ADC_IRQ_EN_W<'_, 2>
Bit 2 - ADC FIFO Data Available IRQ Enable
sourcepub fn adc_drq_en(&mut self) -> ADC_DRQ_EN_W<'_, 3>
pub fn adc_drq_en(&mut self) -> ADC_DRQ_EN_W<'_, 3>
Bit 3 - ADC FIFO Data Available DRQ Enable
sourcepub fn rx_fifo_trg_level(&mut self) -> RX_FIFO_TRG_LEVEL_W<'_, 4>
pub fn rx_fifo_trg_level(&mut self) -> RX_FIFO_TRG_LEVEL_W<'_, 4>
Bits 4:11 - RX FIFO Trigger Level (RXTL[5:0])
Interrupt and DMA request trigger level for RX FIFO normal condition IRQ/DRQ generated when WLEVEL > RXTL[5:0]
sourcepub fn rx_sample_bits(&mut self) -> RX_SAMPLE_BITS_W<'_, 16>
pub fn rx_sample_bits(&mut self) -> RX_SAMPLE_BITS_W<'_, 16>
Bit 16 - Receiving Audio Sample Resolution
sourcepub fn rx_sync_en(&mut self) -> RX_SYNC_EN_W<'_, 20>
pub fn rx_sync_en(&mut self) -> RX_SYNC_EN_W<'_, 20>
Bit 20 - Audiocodec RX Synchronize Enable
sourcepub fn rx_sync_en_start(&mut self) -> RX_SYNC_EN_START_W<'_, 21>
pub fn rx_sync_en_start(&mut self) -> RX_SYNC_EN_START_W<'_, 21>
Bit 21 - The bit takes effect only when RX_SYNC_EN is set to 1. System Domain: Audio codec/I2S0/I2S1/I2S2/DMIC/OWA RX Synchronize Enable Start.
sourcepub fn rx_fifo_mode(&mut self) -> RX_FIFO_MODE_W<'_, 24>
pub fn rx_fifo_mode(&mut self) -> RX_FIFO_MODE_W<'_, 24>
Bit 24 - RX FIFO Output Mode (Mode 0, 1)
For 20-bit received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[19:0], 12’h0}
Mode 1: RXDATA[31:0] = {12{FIFO_O[19]}, FIFO_O[19:0]}
For 16-bit received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[19:4], 16’h0}
Mode 1: RXDATA[31:0] = {16{FIFO_O[19]}, FIFO_O[19:4]}
sourcepub fn adcdfen(&mut self) -> ADCDFEN_W<'_, 25>
pub fn adcdfen(&mut self) -> ADCDFEN_W<'_, 25>
Bit 25 - ADC FIFO delay function for writing data after EN_AD
sourcepub fn adcfdt(&mut self) -> ADCFDT_W<'_, 26>
pub fn adcfdt(&mut self) -> ADCFDT_W<'_, 26>
Bits 26:27 - ADC FIFO delay time for writing data after EN_AD