Module d1_pac::csic::csic_parser0::prs_ncsic_if_cfg

Parser NCSIC Interface Configuration Register

Structs

• PRS_NCSIC_IF_CFG_SPEC
  Parser NCSIC Interface Configuration Register
• R
  Register prs_ncsic_if_cfg reader
• W
  Register prs_ncsic_if_cfg writer

Enums

• CLK_POL_A
  Data clock type
• CSI_IF_A
  Value on reset: 0
• DDR_SAMPLE_MODE_EN_A
  Value on reset: 0
• FIELD_A
  Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)
• FIELD_DT_MODE_A
  only valid when CSI_IF is YUB and source type is interlaced
• HREF_POL_A
  Href polarity
• IF_DATA_WIDTH_A
  Value on reset: 0
• INPUT_SEQ_A
  Input data sequence, only valid for YUV422 and YUV420 input format
• SEQ_8PLUS2_A
  When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual CSI data bus according to these sequences
• SOURCE_TYPE_A
  Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3
• VREF_POL_A
  Vref polarity
• YUV420_LINE_ORDER_A
  Value on reset: 0

Type Aliases

• CLK_POL_R
  Field clk_pol reader - Data clock type
• CLK_POL_W
  Field clk_pol writer - Data clock type
• CSI_IF_R
  Field csi_if reader -
• CSI_IF_W
  Field csi_if writer -
• DDR_SAMPLE_MODE_EN_R
  Field ddr_sample_mode_en reader -
• DDR_SAMPLE_MODE_EN_W
  Field ddr_sample_mode_en writer -
• FIELD_DT_MODE_R
  Field field_dt_mode reader - only valid when CSI_IF is YUB and source type is interlaced
• FIELD_DT_MODE_W
  Field field_dt_mode writer - only valid when CSI_IF is YUB and source type is interlaced
• FIELD_DT_PCLK_SHIFT_R
  Field field_dt_pclk_shift reader - Only for vsync detected field mode, the odd field permitted pclk
• FIELD_DT_PCLK_SHIFT_W
  Field field_dt_pclk_shift writer - Only for vsync detected field mode, the odd field permitted pclk
• FIELD_R
  Field field reader - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)
• FIELD_W
  Field field writer - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)
• HREF_POL_R
  Field href_pol reader - Href polarity
• HREF_POL_W
  Field href_pol writer - Href polarity
• IF_DATA_WIDTH_R
  Field if_data_width reader -
• IF_DATA_WIDTH_W
  Field if_data_width writer -
• INPUT_SEQ_R
  Field input_seq reader - Input data sequence, only valid for YUV422 and YUV420 input format
• INPUT_SEQ_W
  Field input_seq writer - Input data sequence, only valid for YUV422 and YUV420 input format
• SEQ_8PLUS2_R
  Field seq_8plus2 reader - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual CSI data bus according to these sequences
• SEQ_8PLUS2_W
  Field seq_8plus2 writer - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual CSI data bus according to these sequences
• SOURCE_TYPE_R
  Field source_type reader - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3
• SOURCE_TYPE_W
  Field source_type writer - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3
• VREF_POL_R
  Field vref_pol reader - Vref polarity
• VREF_POL_W
  Field vref_pol writer - Vref polarity
• YUV420_LINE_ORDER_R
  Field yuv420_line_order reader -
• YUV420_LINE_ORDER_W
  Field yuv420_line_order writer -