Module d1_pac::csic::csic_top::csic_ptn_ctrl

CSIC Pattern Control Register

Structs

• CSIC_PTN_CTRL_SPEC
  CSIC Pattern Control Register
• R
  Register csic_ptn_ctrl reader
• W
  Register csic_ptn_ctrl writer

Enums

• PTN_GEN_DATA_WIDTH_A
  Value on reset: 0
• PTN_MODE_A
  Pattern mode selection
• PTN_PORT_SEL_A
  Pattern Generator output port selection

Type Aliases

• PTN_GEN_CLK_DIV_R
  Field ptn_gen_clk_div reader - Packet generator clock divider
• PTN_GEN_CLK_DIV_W
  Field ptn_gen_clk_div writer - Packet generator clock divider
• PTN_GEN_DATA_WIDTH_R
  Field ptn_gen_data_width reader -
• PTN_GEN_DATA_WIDTH_W
  Field ptn_gen_data_width writer -
• PTN_GEN_DLY_R
  Field ptn_gen_dly reader - Clocks delayed before pattern generating start.
• PTN_GEN_DLY_W
  Field ptn_gen_dly writer - Clocks delayed before pattern generating start.
• PTN_MODE_R
  Field ptn_mode reader - Pattern mode selection
• PTN_MODE_W
  Field ptn_mode writer - Pattern mode selection
• PTN_PORT_SEL_R
  Field ptn_port_sel reader - Pattern Generator output port selection
• PTN_PORT_SEL_W
  Field ptn_port_sel writer - Pattern Generator output port selection