Struct d1_pac::csic::csic_top::CSIC_TOP

source · 
#[repr(C)]
pub struct CSIC_TOP {
Show 15 fields
    pub csic_top_en: CSIC_TOP_EN,
    pub csic_ptn_gen_en: CSIC_PTN_GEN_EN,
    pub csic_ptn_ctrl: CSIC_PTN_CTRL,
    pub csic_ptn_len: CSIC_PTN_LEN,
    pub csic_ptn_addr: CSIC_PTN_ADDR,
    pub csic_ptn_isp_size: CSIC_PTN_ISP_SIZE,
    pub csic_dma_input_sel: [CSIC_DMA_INPUT_SEL; 2],
    pub csic_bist_cs: CSIC_BIST_CS,
    pub csic_bist_control: CSIC_BIST_CONTROL,
    pub csic_bist_start_addr: CSIC_BIST_START_ADDR,
    pub csic_bist_end_addr: CSIC_BIST_END_ADDR,
    pub csic_bist_data_mask: CSIC_BIST_DATA_MASK,
    pub csic_mbus_req_max: CSIC_MBUS_REQ_MAX,
    pub csic_mulf_mod: CSIC_MULF_MOD,
    pub csic_mulf_int: CSIC_MULF_INT,
    /* private fields */

}
Expand description

Register block

Fields§

§csic_top_en: CSIC_TOP_EN

0x00 - CSIC TOP Enable Register

§csic_ptn_gen_en: CSIC_PTN_GEN_EN

0x04 - CSIC Pattern Generation Enable Register

§csic_ptn_ctrl: CSIC_PTN_CTRL

0x08 - CSIC Pattern Control Register

§csic_ptn_len: CSIC_PTN_LEN

0x20 - CSIC Pattern Generation Length Register

§csic_ptn_addr: CSIC_PTN_ADDR

0x24 - CSIC Pattern Generation Address Register

§csic_ptn_isp_size: CSIC_PTN_ISP_SIZE

0x28 - CSIC Pattern ISP Size Register

§csic_dma_input_sel: [CSIC_DMA_INPUT_SEL; 2]

0xa0..0xa8 - CSIC DMA[i] Input Select Register

§csic_bist_cs: CSIC_BIST_CS

0xdc - CSIC BIST CS Register

§csic_bist_control: CSIC_BIST_CONTROL

0xe0 - CSIC BIST Control Register

§csic_bist_start_addr: CSIC_BIST_START_ADDR

0xe4 - CSIC BIST Start Address Register

§csic_bist_end_addr: CSIC_BIST_END_ADDR

0xe8 - CSIC BIST End Address Register

§csic_bist_data_mask: CSIC_BIST_DATA_MASK

0xec - CSIC BIST Data Mask Register

§csic_mbus_req_max: CSIC_MBUS_REQ_MAX

0xf0 - CSIC MBUS REQ MAX Register

§csic_mulf_mod: CSIC_MULF_MOD

0x100 - CSIC Multi-Frame Mode Register

§csic_mulf_int: CSIC_MULF_INT

0x104 - CSIC Multi-Frame Interrupt Register

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