Struct d1_pac::rtc::rtc_spi_clk_ctrl::R

pub struct R(/* private fields */);

Register rtc_spi_clk_ctrl reader

Implementations

impl R

pub fn rtc_spi_clk_div(&self) -> RTC_SPI_CLK_DIV_R

Bits 0:4 - RTC Reg CFG SPI Clock Divider: M

Actual SPI Clock = AHBS1/(M+1), (0 to 15) The default frequency of AHBS1 is 200 MHz, and the default frequency of SPI Clock is 20 MHz.

Note: The SPI clock can not exceed 50 MHz, or else the RTC register may be abnormal.

pub fn rtc_spi_clk_gating(&self) -> RTC_SPI_CLK_GATING_R

Bit 31 - RTC Reg CFG SPI Clock Gating

Before configurating RTC register, the clock divider of SPI needs be configured firstly, then clock gating needs be enabled.

Note: Frequency division and clock gating can not be set at the same time.

Methods from Deref<Target = R<RTC_SPI_CLK_CTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<RTC_SPI_CLK_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<RTC_SPI_CLK_CTRL_SPEC>> for R

fn from(reader: R<RTC_SPI_CLK_CTRL_SPEC>) -> Self

Converts to this type from the input type.