Struct d1_pac::rtc::rtc_spi_clk_ctrl::W

pub struct W(/* private fields */);

Register rtc_spi_clk_ctrl writer

Implementations

impl W

pub fn rtc_spi_clk_div(&mut self) -> RTC_SPI_CLK_DIV_W<'_, 0>

Bits 0:4 - RTC Reg CFG SPI Clock Divider: M

Actual SPI Clock = AHBS1/(M+1), (0 to 15) The default frequency of AHBS1 is 200 MHz, and the default frequency of SPI Clock is 20 MHz.

Note: The SPI clock can not exceed 50 MHz, or else the RTC register may be abnormal.

pub fn rtc_spi_clk_gating(&mut self) -> RTC_SPI_CLK_GATING_W<'_, 31>

Bit 31 - RTC Reg CFG SPI Clock Gating

Before configurating RTC register, the clock divider of SPI needs be configured firstly, then clock gating needs be enabled.

Note: Frequency division and clock gating can not be set at the same time.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<RTC_SPI_CLK_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<RTC_SPI_CLK_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<RTC_SPI_CLK_CTRL_SPEC>> for W

fn from(writer: W<RTC_SPI_CLK_CTRL_SPEC>) -> Self

Converts to this type from the input type.