Struct d1_pac::tcon_lcd0::fsync_gen_dly::FSYNC_GEN_DLY_SPEC

pub struct FSYNC_GEN_DLY_SPEC;

FSYNC_GEN_DLY

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see fsync_gen_dly module

Trait Implementations

impl Readable for FSYNC_GEN_DLY_SPEC

read() method returns fsync_gen_dly::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for FSYNC_GEN_DLY_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for FSYNC_GEN_DLY_SPEC

reset() method sets fsync_gen_dly to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <tcon_lcd0::fsync_gen_dly::FSYNC_GEN_DLY_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for FSYNC_GEN_DLY_SPEC

write(|w| ..) method takes fsync_gen_dly::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <tcon_lcd0::fsync_gen_dly::FSYNC_GEN_DLY_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <tcon_lcd0::fsync_gen_dly::FSYNC_GEN_DLY_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1